RTU 2024 Syllabus (Released)- Get Section & Subject Wise RTU Syllabus

RTU 2024 Syllabus has been released by official authority. RTU is the associated university which has been built in Kota, Rajasthan. It was originated in 2006 through the Government of Rajasthan. The university allies with 130 engineering colleges, 41 MCA colleges, and 95 MBA Colleges.

RTU 2024 Syllabus:

Candidates must check the Syllabus for RTU 2024 from below:

B.Tech (Electrical Engineering):

Junction Diodes: Formation of homogenous and heterojunction diodes and their energy band diagrams, calculation of contact potential and depletion width, V-I characteristics, Small-signal models of the diode, Diode as a circuit element, diode parameters and load line concept, C-V characteristics, and dopant profile. Applications of diodes in the rectifier, clipping, clamping circuits, and voltage multipliers. Transient behavior of PN diode. Breakdown diodes, Schottky diodes, and Zener diode as the voltage regulator. Construction, characteristics and operating principle of UJT.

Semiconductor Physics: Mobility and conductivity, charge densities in a semiconductor, Fermi Dirac distribution, Fermi-Dirac statistics and Boltzmann an approximation to the Fermi-Dirac statistics, carrier concentrations and Fermi levels in Semiconductor. Generation and recombination of charges, diffusion and continuity equation, transport equations, Mass action Law, Hall effect.

Transistors: Characteristics, Current Components, Current Gains: alpha and beta. Variation of transistor parameter with temperature and current level, Operating point, Hybrid model, DC model of the transistor, h-parameter equivalent circuits.CE, CB and CC configuration DC and AC analysis of single-stage CE, CC (Emitter follower) and CB amplifiers AC & DC load line, Ebers-Moll model. Biasing & stabilization techniques. Thermal runaway, Thermal stability.

Computer Architecture:

Unit-1:

• Introduction to Computer Architecture and Organization: Von Neuman Architecture,  Flynn  Classification.
• Register Transfer and Micro-operations: Register transfer language, Arithmetic Micro-operations, Logic Micro-operations, Shift Micro-operations, Bus and memory transfers.
• Computer Organization  and Design:  Instruction  cycle,  computer  registers, common bus system, computer instructions, addressing modes, design of a basic computer

Unit-2:

• Central Processing Unit: General register organization, stack organization, Instruction  formats,  Data  transfer  and  manipulation,  program control. RISC,  CISC characteristics.
• Pipeline and Vector processing: Pipeline structure, speedup, efficiency, throughput, and bottlenecks.  Arithmetic pipeline and  Instruction pipeline.

Unit-3:

• Computer Arithmetic: Adder, Ripple carry Adder, carry look Ahead Adder, Multiplication: Add and Shift, Array multiplier and Booth Multiplier, Division: restoring and  Non-restoring  Techniques.
• Floating-Point  Arithmetic:  Floating-point representation,  Add,  Subtract,  Multiplication,  Division.

Unit-4:

• Memory Organization: RAM, ROM, Memory Hierarchy, Organization, Associative memory, Cache memory, and Virtual memory: Paging and Segmentation.

Unit-5:

Input-Output Organization: Input-Output Interface, Modes of Transfer, Priority Interrupt,  DMA,  IOP processor.

Telecommunication Fundamentals:

Unit-1:

• Data Transmission: Terminology, Frequency, spectrum, bandwidth, analog & digital transmission, Transmission impairments, channel capacity, Transmission Media.
• Wireless Transmission: Antenna and antenna gain. Network Reference Models (OSI/ISO and  TCP/IP)
• Physical Layer: Line Encoding Schemes. The concept of the bit period, the effect of clock skew, Synchronous, and Asynchronous communication.
• Data Link Layer: Functions of the data link layer and design  issues
• Flow Control: Flow control in lossless and lossy channels using stop-and-wait, sliding window protocols. Performance of protocols used for flow control.

Unit-2:

• Error Control Coding: Error Detection, Two Dimensional  Parity  Checks,  and Internet Checksum. Polynomial Codes, Standardized polynomial codes, error detecting capability of polynomial codes. Linear codes, the performance of linear codes, error detection & correction using linear systems.
• Data Link Control: HDLC & PPP including frame structures.
• MAC sublayer: Channel Allocation Problem, Pure and slotted Aloha, CSMA, CSMA/CD, collision-free multiple access. Throughput analysis of pure and slotted Aloha. Ethernet Performance.

Unit-3:

• Wireless LAN: Hidden node and Exposed node Problems, RTS/CTS based protocol, 802.11 Architecture, a protocol stack, Physical layer, MAC   Sublayer.
• Bluetooth Architecture and Protocol Stack Data Link Layer Switching: Bridges (Transparent, Learning and Spanning Tree), Virtual LANs

Unit-4:

• Multiplexing: Frequency division, time division (Synchronous and statistical) multiplexing. ADSL, DS1 and DS3  carriers.
• Multiple Accesses: TDMA frame structure, TDMA Burst Structure, TDMA Frame efficiency, TDMA Superframe structure, Frame acquisition, and synchronization, Slip rate in digital terrestrial networks.
• Switching: Qualitative description of Space division, time division, and space-time- space division switching.

Unit-5:

• Spread Spectrum Techniques: Direct sequence(DSSS) & frequency hopping(FHSS); Performance consideration in DSSS & FHSS;
• Code Division Multiple Access (CDMA): frequency & channel specifications, forward & reverse CDMA channel, pseudo-noise (PN) sequences, m-sequence, gold sequence, orthogonal code, gold sequences, Walsh codes, synchronization, power control, handoff, the capacity of a CDMA system, IMT-2000, WCDM.

Database Management System:

Unit-1:

Introduction to Database System: Overview and History of DBMS. File System v/s DBMS.An advantage of DBMS Describing and Storing Data in a  DBMS. Queries in DBMS. Structure of a  DBMS.

Unit-2:

Entity-Relationship Model: Overview of  Data  Design  Entities,  Attributes and Entity Sets, Relationship and Relationship Sets. Features of the ER Model- Key Constraints, Participation Constraints, Weak Entities, Class Hierarchies, Aggregation, Conceptual Data Base, Design with ER Model-Entity v/s Attribute, Entity vs. Relationship Binary vs. Ternary Relationship and Aggregation v/s ternary Relationship Conceptual Design for a Large  Enterprise.

Unit-3:

Relationship Algebra & Calculus: Relationship  Algebra Selection and Projection, Set Operations, Renaming, Joints, Division, Relation Calculus, Expressive Power of Algebra and  Calculus.

Unit-4:

SQL Queries Programming & Triggers:  The Forms of a  Basic SQL Query, Union, Intersection and Except, Nested Queries, Correlated Nested Queries, Set-Comparison Operations, Aggregate Operators, Null Values and Embedded SQL, Dynamic SQL, ODBC and JDBC, Triggers and Active  Databases.

Unit-5:

Schema Refinement & Normal Forms: Introductions to Schema Refinement, Functional Dependencies, Boyce-Codd Normal Forms, Third Normal  Form, Normalization-Decomposition into BCNF Decomposition into  3-NF.

Advanced-Data Structures:

Unit-1:

• Advanced Trees:  Definitions, Operations on Weight-Balanced  Trees (Huffman Trees), 2-3 Trees and Red-Black Trees. Dynamic  Order  Statistics,  Interval  Tree;  Dictionaries.

Unit-2:

• Mergeable Heaps: Mergeable     Heap    Operations,     Binomial    Trees, Implementing Binomial Heaps and its Operations, 2-3-4. Trees and 2-3-4 Heaps. Amortization analysis and Potential Function of Fibonacci Heap, Implementing Fibonacci  Heap.

Unit-3:

• Graph Theory Definitions: Definitions of Isomorphic  Components. Circuits, Fundamental Circuits, Cut-sets. Cut- Vertices Planer and Dual graphs, Spanning  Trees, Kuratovski ’s two Graphs.
• Graph Theory Algorithms: Algorithms for Connectedness, Finding all Spanning Trees in a Weighted Graph, Breadth-First & Depth First Search, Topological  Sort,  Strongly  Connected Components & Articulation   Point. Single  Min-Cut Max-Flow theorem of  Network  Flows.   Ford-Fulkerson   Max-Flow  Algorithms.

Unit-4:

• Sorting network: Comparison network, zero-one principle, bitonic sorting, and merging network sorter. Priority Queues and Concatenable Queues using 2-3  Trees. Operations on Disjoint sets and its union-find problem,  Implementing   Sets.

Unit-5:

• Number Theoretic Algorithm: Number theoretic notions,  Division theorem, GCD, recursion, Modular arithmetic, Solving Modular Linear equation, Chinese Remainder Theorem, the power of an element, Computation of Discrete Logarithms,  Primality Testing and Integer Factorization.

Operating System:

Unit-1:

Introduction and need of the operating system, layered architecture/ logical structure of the operating system, Type of OS, the operating system as the resource manager and virtual machine, OS services,  BIOS, System  Calls/Monitor  Calls,  Firmware-  BIOS,  Boot Strap Loader.

Process management- Process model, creation,  termination,  states  &  transitions,  hierarchy, context switching, process implementation, process control block, Basic System calls- Linux & Windows. Threads- processes versus threads,  threading,  concepts,  models,  kernel  & user-level threads,  thread usage,  benefits, multithreading models.

Unit-2:

Interprocess communication- Introduction to message passing, Race condition,   critical section problem, mutual exclusion with busy waiting- disabling interrupts, lock variables, strict alteration, Peterson’s solution, TSL instructions, busy waiting, sleep and wakeup calls,  semaphore,   monitors,  classical  IPC problems.

Process  scheduling-  Basic  concepts,  classification,  CPU  and  I/O  bound,   CPU   scheduler- short,  medium,  long-term,   dispatcher,   scheduling:-   preemptive   and  non-preemptive,   Static and Dynamic Priority, Co-operative & Non-cooperative, Criteria/Goals/Performance Metrics, scheduling algorithms- FCFS, SJFS, shortest remaining time, Round robin, Priority scheduling, multilevel  queue scheduling,  multilevel  feedback  queue  scheduling,  Fair  share scheduling.

Unit-3:

Deadlock- System model, resource types, deadlock problem,  deadlock characterization, methods for deadlock handling, deadlock prevention, deadlock avoidance, deadlock detection, recovery from deadlock.

Memory  management-  concepts,  functions,  logical  and  physical  address  space,  address  binding, degree of multiprogramming, swapping, static & dynamic  loading-  creating  a  load module,  loading,  static  &  dynamic  linking,  shared  libraries,   memory   allocation   schemes-  first  fit,  next  fit,  best  fit,  worst  fit,  quick  fit.  Free space management-   bitmap, link list/ free list, buddy ’s system, memory protection and sharing, relocation and address translation.

Unit-4:

Virtual   Memory-   concept,   virtual   address   space,    paging    scheme,    pure    segmentation and segmentation  with  paging  scheme   hardware   support   and   implementation   details, memory fragmentation, demand paging, pre-paging, working set model, page fault frequency, thrashing, page replacement algorithms- optimal, NRU, FIFO, second chance, LRU, LRU- approximation  clock,  WS  clock;   Belady’s   anomaly,   distance   string;   design   issues   for paging system- local versus global allocation  policies,  load  control,  page  size,  separate  instruction  and  data  spaces,  shared  pages, cleaning  policy,  TLB  (  translation  lookaside buffer)  reach,  inverted  page   table,   I/O   interlock,  program  structure,  page  fault  handling, Basic  idea of MM  in Linux &  windows.

Unit-5:

File System: concepts, naming, attributes, operations, types, structure, file organization & access(Sequential,  Direct  ,Index  Sequential) methods, memory-mapped  files, directory structures- one level, two-level, hierarchical/tree, acyclic graph, general graph, file  system  mounting, file sharing, pathname, directory operations, overview of file system in Linux  & windows.

Input/ Output subsystems: concepts, functions/goals, input/ output devices- block and character, spooling, disk structure & operation, disk attachment, disk storage capacity, disk scheduling algorithm-  FCFS,  SSTF, scan scheduling, C-scan schedule.

Digital Logic Design:

Unit-1:

Hardware  Description Languages and their use in digital logic design

• VHDL: Modelling Concepts, Lexical Elements & Syntax Descriptions,  Scalar Data types & Operations, Sequential Statements, Composite Data Types & Operations,  Basic  Modelling  Constructs.
• Case Study:  VHDL Simulation of Ripple  Carry,  & Look Ahead carry Adders.

Unit-2:

• VHDL: Subprograms, Packages & Use Clauses, Aliases, Resolved Signals, Components & Configurations, Generate Statements, Concurrent  Statements. Use of VHDL  in simulation and synthesis.

Unit-3:

• Clocked Sequential circuits. Design steps for synchronous sequential circuits. Design of a sequence detector. Moore and Mealy Machines. Design using JK flip-flops and D flip-flops. State reduction, State assignment, Algorithmic State Charts,  converting  ASM charts to hardware, one-hot state assignment.
• Considerations of clock skew, set-up time, hold-time and other flip-flop parameters, Time constraints. Programmable Logic Devices. Read-only memory. Boolean function implementation through ROM.  PLD,  PGA, PLA, PAL,  FPGA.

Unit-4:

• Event-driven Circuits. The design procedure for asynchronous circuits, stable and unstable states, races, race-free assignments. State reduction of incompletely specified machines. Compatibility and state reduction procedure. Hazards in combinational networks. Dynamic risks, Function Hazards, and Essential Hazards.  Eliminating hazards.

Unit-5:

• Field Programmable Gate Arrays: Introduction, Logic Elements & programmability, Interconnect structures & programmability, Extended Logic Elements, SRAM, Flash Memory & Antifuse Configuration, Case Studies of Altera  Stratix  & Xilinx  Virtex-II pro.
• Technology Mapping for FPGAs: Logic Synthesis, Lookup Table Technology Mapping.

Digital Signal Processing:

Unit-1:

• Introduction: Discrete-time signals and systems,  properties of discrete-time systems, Linear time-invariant systems – discrete time.  Properties of LTI  systems and their block diagrams.  Convolution, Discrete-time systems described by difference equations.

Unit-2:

• Fourier Transform: Discrete-time Fourier transform for periodic and aperiodic signals. Properties of DTFT.
• Z-transform: The region of convergence for the Z- transform.  The  Inverse  Z-transform.   Properties of Z transform.

Unit-3:

• Sampling: Mathematical theory of sampling. Sampling theorem. Ideal & Practical sampling.  Interpolation technique for the reconstruction of a signal from its samples.  Aliasing.  Sampling in freq. Domain.  The sampling of discrete-time signals.

Unit-4:

• Discrete Fourier Transforms: Properties of the  DFT, Linear Convolution using DFT.
• Efficient computation of the DFT: Decimation – in-Time and Decimation-in frequency FFT Algorithms.

Unit-5:

• Filter Design Techniques: Structures for discrete-time systems- Block diagram and signal flow graph representation of LCCD (LCCD – Linear  Constant Coefficient Difference) equations, Basic structures for  IIR  and  FIR systems, Transposed forms.
• Introduction to filter Design: Butterworth  & Chebyshev. IIR filter design by impulse invariance & Bilinear transformation.
• Design of FIR filters by Windowing:  Rectangular,  Hamming  & Kaiser.

Information Theory And Coding:

Unit-1:

Introduction to information theory: Uncertainty, Information, and Entropy, Information measures for continuous random variables, source coding theorem. Discrete Memory fewer channels, Mutual information,  Conditional entropy.

Unit-2:

Source coding schemes for data compaction: Prefix code, Huffman code, Shanon-Fane code & Hempel-Ziv coding channel capacity. Channel coding theorem.  Shannon limit.

Unit-3:

Linear Block Code: Introduction to error connecting codes, coding  & decoding of linear block code, Minimum distance consideration, Conversion of the nonsystematic form of matrices into systematic form.

Unit-4:

Cyclic Code: Code Algebra, Basic properties of Galois fields (GF) polynomial operations over Galois fields, generating cyclic code by generating polynomial,  parity check polynomial. Encoder & decoder for cyclic codes.

Unit-5:

• Convolutional Code: Convolutional encoders of different rates. Code Tree, Trellis, & state diagram.
• Maximum likelihood decoding of convolutional code:  The Viterbi Algorithm fee distance of a convolutional code.